MIPS Instruction Formats

 



R-format Instructions

Name Format Layout Example
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
op rs rt rd shamt funct
addR0 2310 32add $1, $2, $3
adduR0 2310 33addu $1, $2, $3
subR0 2310 34sub $1, $2, $3
subuR0 2310 35subu $1, $2, $3
andR0 2310 36and $1, $2, $3
orR0 2310 37or $1, $2, $3
norR0 2310 39nor $1, $2, $3
sltR0 2310 42slt $1, $2, $3
sltuR0 2310 43sltu $1, $2, $3
sllR0 02110 0sll $1, $2, 10
srlR0 02110 2srl $1, $2, 10
jrR0 31000 8jr $31

NOTE: op is 0, so funct disambiguates

op rs rt rd shamt funct
0 17 18 16 0 32
000000 10001 10010 10000 00000 100000
NOTE: Order of components in machine code is different from assembly code. Assembly code order is similar to C, destination first. Machine code has destination last.
C: a = b + c
assembly code: add $s0, $s1, $s2    # add rd, rs, rt
machine code: 000000 10001 10010 10000 0000 100000
(op rs rt rd shamt funct)

 


I-format Instructions

Name Format Layout Example
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
op rs rt immediate
beqI4 1225 (offset) beq $1, $2, 100
bneI5 1225 (offset) bne $1, $2, 100
addiI8 21100 addi $1, $2, 100
addiuI9 21100 addiu $1, $2, 100
andiI12 21100 andi $1, $2, 100
oriI13 21100 ori $1, $2, 100
luiI15 01100 lui $1, 100
lwI35 21100 (offset) lw $1, 100($2)
swI43 21100 (offset) sw $1, 100($2)
op rs rt immediate
35 19 8 32
100011 10011 01000 0000000000100000
op rs rt immediate
4 8 0 5
000100 01000 00000 0000000000000101

J-format Instructions

Name Format Layout Example
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
op address
jJ2 2500j 10000
jalJ3 2500jal 10000
op address
2 257
000010 00000000000000000100000001


Alyce Brady, Kalamazoo College