Lab A: Observing Data Flow within the Data Path Simulator (PathSim)

Originally by Dr. Dalton R. Hunkins. Adapted by Nathan Sprague 2008.

Goal:

With the completion of this lab you will understand the values placed on lines in the data path as discussed in sections 5.1 through 5.4

Steps

1. Use your browser to open the data path simulator PathSim.html.

2. Select and copy the snippet of assembly code appearing below and paste it into the Instruction Input box in PathSim. The Instruction Input box is a text box and, therefore, you can do some text-editing within the box. Next, assemble the set of instructions by pressing the Assemble button. The snippet of code is written intentionally with two syntax errors. Thus, when you assemble the code, an alert box will popup, showing a line containing an error. The PathSim assembler is a "first error and out" assembler and, therefore, you will only see one error at a time. Now, fix the first error and (re-)assemble the edited code. Since there is another error in the code, you will see another alert box showing the second error. Fix the second error, assemble the edited code and it should now assemble successfully. If another error should appear on the last line, it is due to a missing end-of-line marker. PathSim expects that ALL lines are terminated with an end-of-line.

3. Select and copy the three lines of words with addresses given after the comment #Data Memory and paste them into the Data Input box. Press the Load button within the Data Input box; the data should load successfully. If not, check to see that there are no empty lines nor spaces within the text. Also, make sure the third line is terminated with an end-of-line marker.

4. Select and copy the one word with register number appearing after the comment #Register Values and paste it into the Register Input box. Press the Load button within the Register Input box; the word should load successfully into the specified register. If not, make sure that the line is terminated with an end-of-line marker and there are not empty lines nor spaces.

5. Place the mouse over the rectangle marked PC shown in the data path diagram and left-click the mouse. Left-clicking on PC steps through the machine instructions that were assembled from the snippet of assembly code, one instruction per click. As you step through the code, place the mouse over data lines shown in the data path diagram and left-click the mouse. A popup box will appear showing the value (in hex) which is on that line.

   At the bottom of this page there are tables with spaces for values on some of the PathSim lines. Complete these tables in two steps. First, cross out all fields that are not relevant for the current instruction. For example, the outputs of the sign extension unit at the bottom will be ignored in an R-Format instruction, therefore all of the inputs and outputs to that unit should be crossed out. On the other hand, all of the inputs and outputs of the ALU controller will be relevant. After you have crossed out the irrelevant fields, fill in the remaining fields with values from the appropriate PathSim lines.

6. Close the browser and PathSim after you have stepped through each of the machine instructions and recorded your observed values. You have completed this lab exercise.

   
   #Assembly Code
   lw   $a0, 0($t1)
   lw   $a1, 4($t1)
   lw   $a2 8($t1)
   add  $t2, $a0, $a1
   addi $t2, $t2, 2
   beq  $t2, $zero, 1   # No labels.  Branch offsets must be provided in hex.
   and  $t4, $a0, $a3, $a3
   or   $t5, $a1, $a2
   sw   $t5, 1c($t1)    # Again, offset is in hex.
   
   #Data Memory
   8:00000128
   C:0000a35a
   10:0000f696
   
   #Register Values
   9:00000008
   
   

   
   

   add $t2, $a0, $a1
   	WriteReg Mux	Registers	Sign Ext	ALU Input 2 Mux	ALU Cont	ALU
   Input	I[20-16]	I[25-21]	I[15-0]	ReadData2	I[5-0]	ReadData 1
   Input	I[15-11]	I[20-16]		SignExtOut		ALU Input 2 Mux Out
   Input		WriteReg
   Input		WriteData
   Control	RegDst	RegWrite		ALUSrc	ALUOp	ALUControl
   Output	WriteReg	ReadData1	SignExtOut	ALU Input2 Mux Out	ALUControl	Zero
   Output		ReadData2				ALUResult

   
   
   

   addi $t2, $t2, 2
   	WriteReg Mux	Registers	Sign Ext	ALU Input 2 Mux	ALU Cont	ALU
   Input	I[20-16]	I[25-21]	I[15-0]	ReadData2	I[5-0]	ReadData 1
   Input	I[15-11]	I[20-16]		SignExtOut		ALU Input 2 Mux Out
   Input		WriteReg
   Input		WriteData
   Control	RegDst	RegWrite		ALUSrc	ALUOp	ALUControl
   Output	WriteReg	ReadData1	SignExtOut	ALU Input2 Mux Out	ALUControl	Zero
   Output		ReadData2				ALUResult

   
   
   

   beq $t2, $zero, 1
   	WriteReg Mux	Registers	Sign Ext	ALU Input 2 Mux	ALU Cont	ALU
   Input	I[20-16]	I[25-21]	I[15-0]	ReadData2	I[5-0]	ReadData 1
   Input	I[15-11]	I[20-16]		SignExtOut		ALU Input 2 Mux Out
   Input		WriteReg
   Input		WriteData
   Control	RegDst	RegWrite		ALUSrc	ALUOp	ALUControl
   Output	WriteReg	ReadData1	SignExtOut	ALU Input2 Mux Out	ALUControl	Zero
   Output		ReadData2				ALUResult

   
   
   

   lw $a2, 8($t1)
   	WriteReg Mux	Registers	Sign Ext	ALU Input 2 Mux	ALU Cont	ALU
   Input	I[20-16]	I[25-21]	I[15-0]	ReadData2	I[5-0]	ReadData 1
   Input	I[15-11]	I[20-16]		SignExtOut		ALU Input 2 Mux Out
   Input		WriteReg
   Input		WriteData
   Control	RegDst	RegWrite		ALUSrc	ALUOp	ALUControl
   Output	WriteReg	ReadData1	SignExtOut	ALU Input2 Mux Out	ALUControl	Zero
   Output		ReadData2				ALUResult