Summary of Datapath Characteristics

Single-cycle

• every instruction takes 1 clock tick, i.e., 1 cycle
     this implies that all instructions take the same amount of time
• each stage takes only the amount of time it requires (there's no reason to slow down register reads, for example, just because memory access is slow)
• each instruction finishes completely before the next instruction starts

Multi-cycle

• every stage takes 1 clock tick, i.e., 1 cycle
     this implies that all stages must take the same amount of time
• each instruction uses only the stages it needs
• each instruction finishes completely before the next instruction starts

Pipelined

• every stage takes 1 clock tick, i.e., 1 cycle
     this implies that all stages must take the same amount of time
• each instruction must "use" (or at least wait around for) every stage (because otherwise an instruction and the instructions that follow would get in each other's way)
• as each instruction goes to the next stage, another instruction starts at the beginning of the pipeline